Hierarchical physical implementation of digital integrated circuits involves partitioning a full netlist of the integrated circuit into partitions (e.g., modules) that will be physically implemented separately. A top-level design team gives each partition a fixed physical boundary. The top-level design team assigns each partition to a lower-level physical design team, which physically designs the given partition.
Each physical design team is constrained. Only the instances (e.g., cells) and the nets (e.g., wires) that belong to the partition's netlist can be placed and routed inside the partition's boundary. In a channel-less floorplan the partitions have boundaries which are fully abutted with the neighboring partitions or the die. Fully abutted means there are no routing resources available (e.g., no channels) between partitions to implement the “top” nets. The top nets are the nets that are not logically contained inside any single partition.
Accordingly, the top-level design team must coordinate the efforts of the individual physical design teams. Although the individual physical design teams are tasked with designing a given partition, the partitions are connected and communicate to advance the overall objectives of the integrated circuit. Where there is a channel-less floorplan with fully abutted neighboring partitions, the top-level design team coordinates the proper connections between partitions.
A challenge for the top-level design team is making sure that the logical design of the integrated circuit can be implemented properly in the physical design of the integrated circuit. For example, the logical design needs to be translated into proper port connections between abutting modules, which the physical design teams will implement. There are many port connections that need to be coordinated correctly. Such a task can be tedious and time-consuming and is further complicated when there are multiple identical instantiations of the partitions.